The AMD AM4 socket is a Pin Grid Array (PGA) interface featuring 1,331 pins. Unlike Intel or newer AM5 sockets where pins are on the motherboard, AM4 pins are located directly on the underside of the processor. 1. General Pin Map & Organization
The pins on an AM4 CPU are arranged in concentric rings and are densely packed to support high-speed data transfer. While a full official pin-by-pin spreadsheet is typically restricted to developers, the layout generally follows these functional groupings:
VSS (Ground): The most common pin type, providing a return path for electrical current.
VCC/VDD (Power): Supplies voltage to the CPU cores, SOC (System on Chip), and memory controller.
DDR4 Memory Interface: Dedicated pins for communicating with RAM (AM4 supports dual-channel DDR4).
PCIe Lanes: Direct connections for graphics cards and NVMe storage. am4 pin layout
Display/IO: Pins for integrated graphics (APUs) and auxiliary inputs like USB and SATA. 2. Physical Keying & Alignment
To prevent incorrect installation, the AM4 layout is keyed with missing pins in specific corners.
The Golden Triangle: One corner of the CPU features a small gold triangle. This must align with the corresponding triangle or notch on the corner of the AM4 motherboard socket.
Pin-Free Zones: If you look at the bottom of an AM4 chip, you will notice a 2x2 grid of "missing" pins in the top-left corner (relative to the triangle) and 3-pin gaps in others. This ensures the CPU only drops into the socket when oriented correctly.
AMD's Socket AM4 (PGA 1331) was the cornerstone of the Ryzen platform from 2016 until the launch of AM5 in 2022. Unlike modern Intel sockets or the newer AM5, which use Land Grid Array (LGA) where pins are on the motherboard, AM4 uses a Pin Grid Array (PGA) where 1,331 physical pins are located on the underside of the processor. Functional Groups of the AM4 Pin Layout The AMD AM4 socket is a Pin Grid
The 1,331 pins are not identical; they are organized into specific functional "zones" that handle power, data, and communication.
AM4 socket Pin Grid Array (PGA) layout with 1,331 pins . Unlike newer AM5 or Intel LGA sockets, the pins are located on the underside of the processor itself rather than the motherboard socket. TechPowerUp Key Technical Specifications Pin Count: 1,331 pins (a significant increase from AM3+'s 942 pins). Dimensions: The package is square, measuring 40mm x 40mm These pins are finer and more fragile
than those on older AMD platforms, requiring extreme care during handling. Socket Type:
Zero Insertion Force (ZIF), meaning the CPU should drop into the socket without any pressure. TechPowerUp Functional Layout Overview
The 1,331 pins are organized to support various high-speed interfaces and power delivery: Memory Support: Dual-channel DDR4 memory. I/O Lanes: Channel A (DIMM A1/A2): Left-side pins
Dedicated PCIe lanes for graphics (typically PCIe 3.0 or 4.0 depending on the chipset/CPU) and NVMe storage. Integrated Chipset:
The processor socket wires out connections normally handled by a southbridge or PCH, as the chipset functions are heavily integrated into the CPU. Orientation Mark: small gold triangle
on one corner of the CPU corresponds to a triangle or notch on the socket to ensure correct installation. Installation & Troubleshooting
| Signal Type | Approx. Pin Count | Description | |-------------|------------------|-------------| | VDD (Core) | ~300 | Core voltage (~0.8–1.5V), distributed around the center | | VSS (Ground) | ~400 | Return current paths, interleaved with power | | VDDCR_SOC | ~60 | Uncore voltage (memory controller, Infinity Fabric, iGPU) | | VDDIO / VDD_MEM | ~40 | Memory I/O voltage (DDR4, 1.2V nominal) | | Infinity Fabric (IF) | ~80 | Differential pairs for chiplet-to-chiplet communication (IFIS) | | DDR4 Channels | ~240 | Two 64-bit channels (plus ECC), each with data, address, command, clock | | PCIe Gen 3/4 | ~200 | Up to 24 lanes (x16 GPU + x4 NVMe + x4 chipset) – each lane: TX+,TX-,RX+,RX- | | SATA / USB / GPIO | ~80 | Multiplexed with PCIe (FCH – Fusion Controller Hub) | | Clock & Reset | ~20 | 100 MHz BCLK, PWR_GOOD, RESET_L, SVI2 telemetry | | SVI2 bus | 2 pins | Serial Voltage Identification Interface 2 (voltage regulation control) | | Misc sense pins | ~10 | VDD_SENSE, VSS_SENSE (remote voltage sensing for VRM) |
The pins responsible for RAM are located along the outer edges of the two longer sides.