In OrCAD Capture 16.6, "making a report" usually refers to generating a Bill of Materials (BOM), which is a list of components used in your schematic. However, you might also need a "Cross Reference" report to find where parts are located.
Here is a step-by-step tutorial on how to generate the most common reports.
Step 4.1: Board Setup
File > New. Give it a name:MyFirstBoard.brd.Setup > Design Parameters: Set the Units toMillimeters(or Mils if you prefer imperial). Set Accuracy to4.Setup > Cross-section: Define your stackup. For a 2-layer board: Top (Signal/Cu), Dielectric, Bottom (Signal/Cu).Setup > Areas > Board Outline: Click the grid to draw a rectangle. ThenShape > Compose Shapeto make it a solid outline.
Part 5: Running DRC and Finishing Up
Before you call your board finished, you must run a physical DRC.
Manufacture > Design Rules Check(DRC).- Click the DRC Action button. Review the report.
- Common errors: Silkscreen overlapping pads (increase clearance) or routing too close to the board edge (change yourRoute Keepin).
Marking Completion:
- Ensure every net trace has no "Unrouted" connections (View > Status).
- Add a Board Outline dimension:
Manufacture > Dimension > Linear.
2. Tutorial 1: Schematic Capture (OrCAD Capture)
Step 2 – Place parts
- Press P or click Place Part
- Libraries:
DISCRETE.OLB,7400.OLB,ANALOG.OLB - Place resistor, capacitor, op-amp, etc.
3.5 Routing
Route → Connect(F2 key) → Click pad → route traces.- Use add vias (right-click during route) to change layers.
- Follow routing guidelines (avoid 90° bends, keep differential pairs together).
Step 3 – Run simulation
- Place voltage/current markers (PSpice → Markers)
- Click Run (blue play button)
- View waveforms in Probe
5.3 Importing Netlist and Footprints
File > Import > Logic.- Import method: “Design entry CIS” (or Allegro).
- Browse to the netlist directory. Click
Import Cadence. - Common error: Missing footprint. Ensure each schematic part has a
PCB Footprintproperty (e.g.,0805for resistors,LED_5MM).
