The Zx Spectrum Ula- How To Design A Microcomputer | -zx Design Retro Computer- 'link'

The book " The ZX Spectrum ULA: How to Design a Microcomputer

" by Chris Smith is a seminal work for retrocomputing enthusiasts, offering a comprehensive, transistor-level deconstruction of the Sinclair ZX Spectrum's custom heart. Published in 2010 by ZX Design and Media, it serves as both a historical record and a practical technical manual for designing 8-bit hardware. The Role of the ULA (Uncommitted Logic Array)

At the center of the ZX Spectrum's design was the Ferranti ULA, a semi-custom logic chip that allowed Clive Sinclair to significantly reduce manufacturing costs. The ULA was responsible for several critical functions:

Video Generation: It read data from video memory and converted it into signals for a television set.

Memory Contention: It managed the priority between the Z80 CPU and video display needs, often pausing the CPU to avoid screen flickering. System Timing: It generated the 3.5 MHz clock for the CPU.

I/O Management: It handled keyboard scanning and audio input/output via the cassette interface. Key Technical Insights from the Book The book " The ZX Spectrum ULA: How

Chris Smith’s work is highly regarded for its reverse-engineering approach, which involves stripping the chip down to its circuit diagrams.

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2. The ULA's Three Jobs (It did everything)

In a normal microcomputer (like the Apple II), these tasks are split across separate chips. In the Spectrum, the ULA ate them all:

The "ULA Replacement" Industry

Because original ULAs are failing (dying due to overheating over 40 years), the retro community has learned exactly "how to design a microcomputer" by reverse-engineering the ULA.

• The vLA82 (by Charlie Ingley): A drop-in, modern CPLD (Complex Programmable Logic Device) replacement. It runs cooler, uses less power, and fixes the "jittery border" of the original.
• The Nebula (by Ben Versteeg): An FPGA solution that emulates the ULA plus extra features (like 64-color mode).
• The PiTubeDirect: Not a replacement, but a co-processor that offloads ULA tasks to a Raspberry Pi.

By cloning the ULA, modern engineers prove that the original design principles—centralized logic, tight coupling of video and CPU, and aggressive cycle stealing—were not mistakes, but intentional choices.

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Chapter 5: The Modern ULA Replacement

You cannot buy a Ferranti ULA today. But you can design its modern equivalent using: The vLA82 (by Charlie Ingley): A drop-in, modern

| Technology | Difficulty | Authenticity | Cost | |------------|------------|--------------|------| | Discrete 74LS logic | Hard (100+ chips) | High | High | | CPLD (e.g., XC2C64A) | Medium | Medium (fast) | Low | | FPGA (e.g., Ice40) | Medium | Low (overkill) | Medium | | Raspberry Pi RP2040 PIO | Low | Low (emulation) | Very Low |

Recommended for your design: Use an Altera/Intel MAX V CPLD or Lattice LCMXO2 FPGA. Program it with ULA-like logic: video timing, contention, and I/O decoding.

High-level architecture for a ULA-style design

Use the following logical blocks when planning a single custom chip to replace discrete logic:

1. Clock & Timing Generator

   • Input: master crystal/clock.
   • Outputs: pixel clock, CPU timing pulses, horizontal/vertical sync, character/t-state counters.

2. Video Fetch & Shift Engine

   • Read pixel bytes and attribute bytes from RAM at appropriate times.
   • Shift register(s) to serialize pixels to analog output.
   • Palette/attribute logic: combine pixel bits with attribute bytes (foreground/background, brightness, flash).

3. Memory Arbiter / Contention Unit

   • Prioritizes video DMA reads during specific t-states while allowing CPU access in others.
   • Inserts wait states for CPU memory accesses when necessary.
   • Ensures DRAM refresh or coordinates refresh cycles.

4. Output Encoder / Composite Generator

   • Convert digital pixel and attribute information into composite/RGB/TTL signals.
   • Add burst/chroma timing if generating color TV signals.

5. I/O Controller

   • Keyboard matrix scan driver and sense logic.
   • Tape interface signal conditioning (pulse generation and detection).
   • Speaker/buzzer control and simple DAC/volume output if required.
   • Peripheral port decoding for joystick/expansion.

6. Interrupt & Control Logic

   • Frame/line interrupt generation (e.g., generate an interrupt at start of frame).
   • Control registers/wires to configure modes (e.g., border color, display enable).
   • Status lines accessible to CPU (e.g., contention flags).

7. Address/Bus Interface

   • Decode address and control bus signals from CPU.
   • Provide minimal glue for ROM/RAM enabling and I/O port decode.

Block diagram (conceptual)

• CPU <-> Bus Buffer/Interface <-> Shared RAM ^ | Memory Arbiter | Video Fetch & Shift -> Output Encoder -> Video Out | I/O Controller -> Keyboard, Tape, Speaker, Ports | Interrupt & Control -> CPU IRQ