# View recent machine checks
mcelog --client
What is Exception 0x12?
In the x64 architecture, the Interrupt Descriptor Table (IDT) holds pointers to code that handles specific events (interrupts and exceptions).
- Vector 18 (0x12 in Hex): This vector is specifically reserved for Machine Check Exceptions.
- Mechanism: Modern CPUs contain specialized registers (MSRs - Model Specific Registers) that monitor the health of the processor. When these sensors detect an anomaly (like a cache error or bus timeout), they trigger the interrupt at vector 0x12.
4.5 Interconnect (CPU-to-CPU) Failure – Multi-Socket Servers
- Symptom: MCE
0x12 with LINK: 0x1 or similar in mcelog.
- Link relevance: UPI/Infinity Fabric link between socket 0 and socket 1.
- Fix: Reseat CPUs, check socket pins, update microcode, disable defective link in BIOS (if supported).